When calculating a delay in a logic circuit in a conventional delay simulation system, a delay analysis library containing circuit connection information and delay information on the basic elements (such as AND elements) of the circuit is used.
The conventional delay analysis library contains connection information as well as delay information which is composed of the delay time of each rise and fall. But, it does not contain logic information on the circuit.
For this reason, the circuit delay analysis uses the worst delay times stored in the delay analysis library, sometimes preventing the delay analysis from being made correctly.
An earlier patent disclosure dealing with delay analysis is found, for example, in Japanese Patent Kokai Publication JP-A No. Hei 1-271869 (1989). In that publication, a propagation delay time calculation method for use in calculating propagation delay times is proposed. In this method, the calculation is made by calculating the load and wiring capacity of the output terminals and the rise time and fall time of each gate.